شبیه سازی cycle-based در سطح انتقال ثبات برای زبان vhdl براساس فرمت میانی chire rtl vhdl cycle-based simulation based on chire

شتاب دهنده شبیه سازی در سطح گیت با استفاده از تکنیک cycle-based

مهندسان در طراحی های بزرگ و پیچیده، قبل از ساخت نمونه فیزیکی و برآورد هزینه و زمان ساخت آن احتیاج به شبیه سازی کامپیوتری سخت افزار دارند. از طرفی سرعت شبیه سازهای متداول برای حجم بزرگ مدار بسیار کند می شود و این به دلیل محاسبات زیادی است که برای بدست آوردن اطلاعات ریز زمانی مدار انجام می شود. اما در بسیاری از موارد یک طراح احتیاج به دیدن درستی عملکرد طرح خود دارد و نه اطلاعات ریز زمانی آن. در ا...

A Formalisation of the VHDL Simulation Cycle

VHDL-based simulation environment for Proteo NoC

The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our Network-on-Chip (NoC) architecture, called "Proteo". In an Intellectual Property (IP) based design methodology also the interconnection structures may be treated as IPs. The Proteo project is aimed at creating a library of pre-designed communication blocks that can be s...

VHDL-based System Simulation and Performance Measurement

This paper describes the techniques employed in the development of a VHDL-based system simulation of the Honeywell RH32 Prototype Development Unit (PDU). The architecture of the PDU is briefly described, and a design process is presented. The system simulation approach is discussed, including simulation model types, their development and validation, and testbench structure. Additionally, techni...

RTL VHDL Behavioral VHDL Test Generator Behavioral VHDL Simulator VHDL Simulator Switch Level

A Visual Simulation Environment for MIPS Based on VHDL

An application to perform a visual simulation of a machine based on MIPS is presented in this paper. The advantage of this system in relation to conventional simulators is that the simulation engine is the result of a real simulation under a VHDL development environment, so that hardware description can be modified and simulated in several ways to probe and study